赖瑾 /Jiin Lai
09/24/2023, 12:50 AM赖瑾 /Jiin Lai
09/24/2023, 2:13 AMjeremy
09/24/2023, 5:09 AM赖瑾 /Jiin Lai
09/25/2023, 6:05 AMzack
09/25/2023, 7:43 AM=== $paramod$5f80bce50362a33e861f1d39e139ffbea0faeb08\sram ===
Number of wires: 25016
Number of wire bits: 25124
Number of public wires: 4160
Number of public wire bits: 4268
Number of memories: 0
Number of memory bits: 0
Number of processes: 0
Number of cells: 25069
...
sky130_fd_sc_hd__and3_2 193
sky130_fd_sc_hd__and3b_2 5
sky130_fd_sc_hd__buf_1 6378
sky130_fd_sc_hd__dfxtp_2 4213
sky130_fd_sc_hd__inv_2 4172
sky130_fd_sc_hd__mux2_2 4448
sky130_fd_sc_hd__mux4_2 1216
sky130_fd_sc_hd__nand2_2 208
...
我猜可能需要手動改 synthesis script?
這裡是有關 yosys memory mapping 的文件
https://yosyshq.readthedocs.io/projects/yosys/en/latest/CHAPTER_Memorymap.html
可能 RTL 內 sram 的描述也要符合文件規範的 memory pattern
附件是完整 area report logzack
09/25/2023, 1:39 PMzack
09/25/2023, 4:11 PM"SYNTH_NO_FLAT": 0
(預設值) 的確會有較小的 total area (-2.66%)
發現設定 openlane config.json "SYNTH_NO_FLAT": 1
yosys 並不是完全不做 flatten 而是延後做的步驟
所以 area report 會產生兩份
第一份是 not_flatten 可以看到個別 module area
yosys 在之後的步驟執行 flatten 會產生第二份 area report 而且會覆蓋第一份...
這時就看不到個別 module area 了
"SYNTH_NO_FLAT": 1
第一份 area report (not_flatten) total area
Chip area for top module '\user_proj_example': 393254.662400
"SYNTH_NO_FLAT": 1
第二份 area report (flatten)
Chip area for module '\user_proj_example': 345168.544000 (-12.23%)
"SYNTH_NO_FLAT": 0
total area (flatten)
Chip area for module '\user_proj_example': 335999.750400 (-2.66%)
赖瑾 /Jiin Lai
09/26/2023, 12:52 AMTony Ho
09/26/2023, 3:06 AMTony Ho
09/26/2023, 9:43 AM(base) tonyho@ubuntu5:~/workspace/fsic/fsic_asic/verif/vsim/rsim$ ./run_xsim system_test111
~/workspace/fsic/fsic_asic/verif/vsim/rsim ~/workspace/fsic/fsic_asic/verif/vsim/rsim
/home/tonyho/workspace/fsic/fsic_asic/src
dos2unix: converting file ../../fsic_fpga/rtl/user/rtl/rtl.f to Unix format...
dos2unix: converting file ../axilite_axis/rtl/rtl.f to Unix format...
dos2unix: converting file ../axis_switch/rtl/rtl.f to Unix format...
dos2unix: converting file ../config_ctrl/rtl/rtl.f to Unix format...
dos2unix: converting file ../fsic_clkrst/rtl/rtl.f to Unix format...
dos2unix: converting file ../io_serdes/rtl/rtl.f to Unix format...
dos2unix: converting file ../logic_analyzer/rtl/rtl.f to Unix format...
dos2unix: converting file ../mprj_io/rtl/rtl.f to Unix format...
Release Date: 09 26
~/workspace/fsic/fsic_asic/verif/vsim/rsim
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/tbuart.v" into library work
INFO: [VRFC 10-311] analyzing module tbuart
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/spiflash.v" into library work
INFO: [VRFC 10-311] analyzing module spiflash
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/fpga.v" into library work
INFO: [VRFC 10-311] analyzing module fpga
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/bfm/fsic_clock.v" into library work
INFO: [VRFC 10-311] analyzing module fsic_clock_div
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/macro/RAM128.pwr.v" into library work
INFO: [VRFC 10-311] analyzing module RAM128
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/verif/vsim/models/macro/RAM256.v" into library work
INFO: [VRFC 10-311] analyzing module RAM256
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/project_define.svh" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/defines.v" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/user_defines.v" into library work
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_master.sv" into library work
INFO: [VRFC 10-311] analyzing module axilite_master
INFO: [VRFC 10-2263] Analyzing SystemVerilog file "/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_slave.sv" into library work
INFO: [VRFC 10-311] analyzing module axilite_slave
ERROR: [VRFC 10-2989] 'bk_busy' is not declared [/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_slave.sv:57]
ERROR: [VRFC 10-2989] 'bk_busy' is not declared [/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_slave.sv:122]
ERROR: [VRFC 10-2989] 'bk_busy' is not declared [/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_slave.sv:194]
ERROR: [VRFC 10-8530] module 'axilite_slave' is ignored due to previous errors [/home/tonyho/workspace/fsic/fsic_asic/dsn/rtl/axilite_slave.sv:9]
error occurred run_xsim
Slack 對話Tony Ho
09/26/2023, 9:44 AMTony Ho
09/29/2023, 3:59 AMTony Ho
09/29/2023, 4:08 AM4200450.000ns MSG top_bench, +1000 cycles, finish_flag=1, repeat_cnt=0042
=============================================================================================
=============================================================================================
=============================================================================================
4200450=> Final result [PASS], check_cnt = 24, error_cnt = 0000
=============================================================================================
=============================================================================================
=============================================================================================
after update fsic_fpga https://github.com/bol-edu/fsic_fpga/commit/cbf29183f077afd46cba9230574c54cff6ebb510
the check_cnt = 0, it is not meet my expectation.Tony Ho
09/29/2023, 6:18 AMTony Ho
09/29/2023, 12:36 PM/ADATA2T/debug/fsic_0929_rtl_sim/caravel_user_project/verilog/rtl/axi_ctrl_logic.sv:290: error: This assignment requires an explicit cast.
zack
09/30/2023, 4:40 AM.axi_awaddr (axi_awaddr_s_awaddr),
input wire [pADDR_WIDTH-1:0] axi_awaddr,
input wire [pADDR_WIDTH-1:0] axi_araddr,
但 config control output 15bit
CFG_CTRL #(.pADDR_WIDTH( 15 ),
.axi_awaddr (axi_awaddr_s_awaddr),
output wire [14: 0] axi_awaddr,
赖瑾 /Jiin Lai
10/01/2023, 1:37 AMTony Ho
10/01/2023, 1:44 PM赖瑾 /Jiin Lai
10/02/2023, 6:31 AMTony Ho
10/03/2023, 1:08 PMTony Ho
10/03/2023, 1:10 PM[WARNING]: OpenLane may not function properly: The version of open_pdks used in building the PDK does not match the version OpenLane was tested on (installed: 0059588eebfc704681dc2368bd1d33d96281d10f, tested: 3af133706e554a740cfe60f21e773d9eaa41838c)
This may introduce some issues. You may want to re-install the PDK by invoking `make pdk`.
[INFO]: Using configuration in '../ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/config.json'...
[INFO]: PDK Root: /ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/dependencies/pdks
[INFO]: Process Design Kit: sky130A
[INFO]: Standard Cell Library: sky130_fd_sc_hd
[INFO]: Optimization Standard Cell Library: sky130_fd_sc_hd
[INFO]: Run Directory: /ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_03_21_11
[INFO]: Preparing LEF files for the nom corner...
[INFO]: Preparing LEF files for the min corner...
[INFO]: Preparing LEF files for the max corner...
[STEP 1]
[INFO]: Running Synthesis (log: ../ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_03_21_11/logs/synthesis/1-synthesis.log)...
[ERROR]: during executing yosys script /openlane/scripts/yosys/synth.tcl
[ERROR]: Log: ../ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/runs/23_10_03_21_11/logs/synthesis/1-synthesis.log
[ERROR]: Last 10 lines:
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_grant [1]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_grant [2]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
No latch inferred for signal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant' from process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048'.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant [0]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant [1]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
Removing init bit 1'0 for non-memory siginal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_grant [2]` in process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:246$1048`.
No latch inferred for signal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_req' from process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:225$1045'.
No latch inferred for signal `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.\shift_hi_req' from process `$paramod$dce6b6a5da2812dbe1b9cc3a0671da84ccd9b415\AXIS_SW.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/sw_caravel.v:225$1045'.
No latch inferred for signal `\axi_ctrl_logic.\axi_interrERROR: No latch inferred for signal `\axi_ctrl_logic.\next_trans' from always_latch process `\axi_ctrl_logic.$proc$/ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/../../verilog/rtl/axi_ctrl_logic.sv:0$161'.
child process exited abnormally
[ERROR]: Creating issue reproducible...
[INFO]: Saving runtime environment...
Tony Ho
10/03/2023, 1:17 PMzack
10/04/2023, 12:47 AM[INFO]: Using configuration in '../ADATA2T/debug/fsic_0929_verify_rtl/caravel_user_project/openlane/user_proj_example/config.json'
config.json 裡面指到的 verilog file 路徑是不是正確
"VERILOG_FILES": ["dir::../../verilog/rtl/defines.v", ...
各 module 版本有沒有同步 因為要手動複製 可能會沒有更新到Tony Ho
10/05/2023, 2:21 AMTony Ho
10/05/2023, 12:22 PMTony Ho
10/13/2023, 9:39 AMTony Ho
10/16/2023, 9:30 AM// AXIS
reg [2:0] axis_rst_nr;
always @(posedge axis_clk or posedge wb_rst)
if( wb_rst )
axis_rst_nr <= 3'b000;
else
axis_rst_nr <= {axis_rst_nr[1:0], 1'b1};
assign axis_rst_n = axis_rst_nr[2];
https://github.com/bol-edu/fsic_fpga/blob/main/rtl/user/fsic_clkrst/rtl/fsic_clkrst.v#L46C1-L54C36Patrick Lin
10/26/2023, 3:34 AMPatrick Lin
10/26/2023, 3:36 AMPatrick Lin
10/26/2023, 3:38 AM