Channels
high-level-synthesis-pqc
fullstack-ic-designer-dev
robotics-computing
fullstack-ic-caravel
random
fullstack-ic-fpga-ip
fullstack-ic-sw
fullstack-ic-system
fullstack-ic-fpga
fullstack-ic-carvel-ip
google-open-source-silicon
pqc-and-homomorphic-encryption
mlb-internal
general
composable-pipeline
soclab-ta
high-level-synthesis-study-group
communication-system
soclab
fsic
qic-discussion
Powered by
#google-open-source-silicon
k
Kevin Jan
11/21/2022, 11:27 AM
Caravel提供Efabless Open MPW的設計template:
https://github.com/efabless/caravel
Caravel是top-level flow會用到skywater-pdk, open_pdks, OpenLane, MPW-Precheck:
https://caravel-harness.readthedocs.io/en/latest/tool-versioning.html
Caravel官方文件:
https://caravel-user-project.readthedocs.io/_/downloads/en/latest/pdf/
OpenLane的架構定義synthesis之後的設計階段:
https://openlane.readthedocs.io/en/latest/flow_overview.html
Caravel的Programming章節有說明用RISC-V toolchain來做測試程式的simulation:
https://caravel-harness.readthedocs.io/en/latest/programming.html
k
Kevin Jan
11/21/2022, 11:27 AM
Efabless官網公開交付的projects的詳細資料:
https://platform.efabless.com/projects/public
k
Kevin Jan
11/21/2022, 11:28 AM
實際操作Caravel (1) 安裝/測試Openlane:
https://openlane.readthedocs.io/en/latest/getting_started/installation_ubuntu.html
(2) 操作Caravel:
https://github.com/efabless/caravel_user_project/blob/main/docs/source/quickstart.rst
(3) 操作錄影:
https://drive.google.com/file/d/1Rz4YVGdCmB5K9tYtKKmxzxnGfzosvHiC/view?usp=sharing
u
赖瑾 /Jiin Lai
11/22/2022, 3:25 AM
Documents related to construction of a testing board. The plan is to insert Caravel test board on connectors of PYNQ-Z2 board. Carvavel Board documentation:
https://github.com/efabless/caravel_board/tree/main/docs
https://github.com/efabless/caravel_board/blob/main/docs/caravel_datasheet.pdf
PYNQ-Z2 Board
https://www.tulembedded.com/FPGA/ProductsPYNQ-Z2.html
PYNQ-Z2 Reference manual
https://www.mouser.com/datasheet/2/744/pynqz2_user_manual_v1_0-1525725.pdf
k
Kevin Jan
11/22/2022, 8:00 AM
基於google-open-source-silicon的線上asic design program
https://www.vlsisystemdesign.com/hdp/
https://www.vlsisystemdesign.com/about-us/
u
赖瑾 /Jiin Lai
11/25/2022, 1:53 PM
附件是 Caravel chip (efabless 標準 MPW chip) 的驗證平台規格。
caravel-validation.pptx