Bridge of Life Education

git clone <https://github.com/The-OpenROAD-Project/OpenLane.git>
    cd OpenLane/
    sudo make
    sudo make test

<http://home.ustc.edu.cn/~louwenqi/reference_books_tools/Computer%20Organization%20and%20Design%20RISC-V%20edition.pdf>

image.png

Here is the chip database directory structure for a common ASIC design for your reference

only /rtl is mandatory for sub-module design

just a suggestion, different company may have different ways in arrange their design file during each phase of a design flow

Hi Kevin
Have you ever doing gate-level simulation of whole chip Caravel SOC based on current eFabless release design?

這裡可以找到整個eFabless Caravel SOC流程中階段驗證的log檔案
<https://github.com/bol-edu/caravel-lab#2-caravel-user-flow>
gate-level simulation的結果與rtl sim印出一樣結果就是跑比較久

I got weird result when simulate the I/O pad and the reset PAD macro didn't work out as expected.
The root cause is a signal "xres_vss_loop) driven by resetb_pad and loopback to itself.

the feekback port is inout type and is is internal pull-up that cause this loopback signal become unknown.

I'm not sure is this a I/O Pad library modeling issue or the pad macro usage problem in chip_io.v of caravel project.

I think I found the root cause, because xsim do not support tranif0 or tranif1 primitive, so I hack the I/O pad model library and replace tranif1/tranfi0 to bufif1/bufif0 primitive which xvlog supported.

since I didn't specify the drive strength of bufif0, so the bus value conflict occurs. after modify the code with drive strength as pull1, then the problem is solved.

line 66 is the original code released by skywater, line 74 is the last correct modeling statement.

我跑eFabless Caravel SOC時還是用官方docker版本 simulator應該是iverilog 10

Yes, 不同的 simulator 問題真的很多

Dear All
In efabless released code, we can see many combination logic coding style is not proper like this below

It cause xsim failed to interpret the true logic function. Please avoid such sequential coding style in combination logic when you are writing your own design.

<@U04R0293ZFH> What do you observe from the xsim?

in simulation, even when if condition is true (&amp; operation), the "next_state" still keep 1'b0. it won't go high

it's simulator dependent, I believe iverilog do not have such problem...

Could you move the F.F definition "txen" earlier than its reference?

<https://veripool.org/papers/Preproc_Good_Evil_SNUGBos10_pres.pdf>

Do anyone have experience on this flow?
<https://antmicro.com/blog/2022/02/simplifying-open-source-sv-synthesis-with-the-yosys-uhdm-plugin/>