Run 23 shows where the corruption happens: when the CPU's modified cache lines are written back out to DDR memory.

What run 23 showed:
- One boot had wrong bytes. Boot 4 delivered wrong bytes to nouveau three times, 4 bytes each (calls 3, 6 and 7).
- The USB driver's check flagged that boot three times. It reported "right in the cache, wrong in memory" three times, each just before one of nouveau's faults.
- Each was the CPU copy into the file handler's buffer. It read back correctly through the cache. After the cache lines were flushed to DDR, memory held the usual wrong-byte pattern.
- The FAT handler's small copies never failed. About 3.5 million copies of 512 bytes per boot, each flushed straight away, came out right.

What this rules out:
- The device and DMA: run 21 showed the device's data was right.
- A stray writer: in run 22 the read-only slot memory took no write fault.
- A bad copy: the data is correct in the cache.

The wrong bytes appear as modified lines travel from the CPU caches through the memory controller into DDR, under boot-time load. In a 64 KB copy, lines also leave the cache by normal eviction, not only by the flush.